DocumentCode
3261257
Title
SASIMI: sparsity-aware simulation of interconnect-dominated circuits with nonlinear devices
Author
Jain, Jitesh ; Cauley, Stephen ; Koh, Cheng-Kok ; Balakrishnan, Venkataramanan
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN
fYear
2006
fDate
24-27 Jan. 2006
Abstract
We present a technique for the fast and accurate simulation of large-scale VLSI interconnects with nonlinear devices, called SASIMI. The numerical efficiency of this technique is realized through linear-algebraic techniques that exploit the sparsity and structure of the matrices that are encountered in VLSI structures. Numerical results show that SASIMI is up to 1400 times as fast as commercial-grade SPICE, for moderate-size circuits, with little sacrifice in simulation accuracy
Keywords
VLSI; circuit simulation; integrated circuit interconnections; linear algebra; SASIMI; SPICE; VLSI interconnects; interconnect-dominated circuits; linear-algebraic techniques; moderate-size circuits; nonlinear devices; sparsity-aware simulation; Circuit simulation; Computational modeling; Computer simulation; Inductance; Integrated circuit interconnections; RLC circuits; SPICE; Sparse matrices; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location
Yokohama
Print_ISBN
0-7803-9451-8
Type
conf
DOI
10.1109/ASPDAC.2006.1594719
Filename
1594719
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