Context-based ASIC synthesis

The authors describe methods for architecture-specific mapping of high-level functions ASICs. The techniques are demonstrated on field programmable gate arrays (FPGAs), but are not limited to those architectures. A network of generic modules provides an input specification from which a delay- and area-efficient logic-level design is synthesized. The methods described herein speed up design time significantly by automatically propagating partial data type specifications, performing architecture-specific design optimizations, and performing context-dependent module synthesis