A modular architecture for BIST of boundary scan boards

Author

Ferreira, José M M ; Pinto, Filipe S. ; Matos, José S.

Author_Institution

FEUP/INESC, Porto, Portugal

fYear

1992

fDate

1-5 Jun 1992

Firstpage

184

Lastpage

188

Abstract

A board-level BIST architecture for boards loaded with ASICs and VLSI components, compliant with the IEEE 1149.1 BST standard, is described. This BIST architecture consists of a test processor core, with an optimized architecture for controlling the board-level BST (boundary scan test) infrastructure, an optional system-level testability bus interface, to be included when a system-level test strategy is to be implemented, and a ROM containing the test program, which is automatically generated by an ATPG tool

Keywords

automatic testing; boundary scan testing; built-in self test; digital circuits; integrated circuit testing; printed circuit testing; ASICs; ATPG tool; BIST; IEEE 1149.1 BST standard; VLSI components; automatic test pattern generator; boundary scan boards; boundary scan test; digital boards; modular architecture; system-level testability bus interface; test processor core; test program ROM; Application specific integrated circuits; Automatic generation control; Automatic test pattern generation; Automatic testing; Binary search trees; Built-in self-test; Code standards; Control systems; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '92, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-2845-6

Type

conf

DOI

10.1109/EUASIC.1992.228027

Filename

228027