Scaling towards 35 nm gate length CMOS

Author

Bin Yu ; Haihong Wang ; Qi Xiang ; An, J.X. ; Joong Jeon ; Ming-Ren Lin

Author_Institution

Technol. Res. Group, Adv. Micro Devices Inc., Sunnyvale, CA, USA

fYear

2001

fDate

12-14 June 2001

Firstpage

9

Lastpage

10

Abstract

We report 35 nm gate length planar CMOS transistors with aggressively scaled gate equivalent oxide thickness (EOT). A nitride/oxynitride (N/O) stack was used as gate dielectric with EOT ranging from 12 /spl Aring/ down to 7 /spl Aring/. The impact of gate scaling on transistor performance, gate tunneling leakage, short-channel effect, and channel carrier mobility is investigated. Excellent control of short-channel effect is achieved for sub-50 nm gate length devices. CV/I delays of 0.89 ps for n-MOSFET and 1.8 ps for p-MOSFET are demonstrated at a supply voltage of 0.85 V.

Keywords

CMOS integrated circuits; MOSFET; carrier mobility; delays; dielectric thin films; integrated circuit design; leakage currents; nanotechnology; tunnelling; 0.85 V; 0.89 ps; 1.8 ps; 35 nm; 50 nm; 7 to 12 angstrom; CMOS gate length; CV/I delays; Si-Si/sub 3/N/sub 4/-SiO/sub 2/-Si; channel carrier mobility; equivalent oxide thickness; gate length; gate length scaling; gate scaling; gate tunneling leakage; n-MOSFET; nitride/oxynitride stack gate dielectric; p-MOSFET; planar CMOS transistors; scaled gate equivalent oxide thickness; short-channel effect; supply voltage; transistor performance; CMOS technology; Delay; High K dielectric materials; Implants; MOSFET circuits; Semiconductor device manufacture; Thermal degradation; Transistors; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-012-7

Type

conf

DOI

10.1109/VLSIT.2001.934921

Filename

934921