A 0.115 /spl mu/m/sup 2/ 8F/sup 2/ DRAM working cell with LPRD (low parasitic resistance device) and poly metal gate technology for gigabit DRAM

Author

Hyunpil Noh ; Woncheol Cho ; Gucheol Jeong ; Min Huh ; Jaemin Ahn ; Ysung Kim ; Suock Jeong ; Seongjoon Lee ; Dongseok Kim ; Hazoong Kim ; Jaebuhm Suh ; Jinwon Park ; Sang-don Lee ; Hee-Koo Yoon

Author_Institution

Memory R&D Div., Hyundai Electron. Co., Ichon, South Korea

fYear

2001

fDate

12-14 June 2001

Firstpage

25

Lastpage

26

Abstract

An 8F/sup 2/ stack DRAM cell, 0.115 /spl mu/m/sup 2/ in size, has been successfully integrated using a selective epitaxial plug scheme for landing plug contacts and poly metal gates and MIM COB capacitors, by which cell working has been proven under easy function check mode. The cell transistor exhibits sufficient saturation current (I/sub OP/) of >40 /spl mu/A with threshold voltage (V/sub tsat/) of 1.0 V.

Keywords

DRAM chips; MIM devices; electric current; electric resistance; electrical contacts; epitaxial growth; integrated circuit interconnections; integrated circuit metallisation; thin film capacitors; 1 V; 40 muA; DRAM working cell; LPRD; MIM COB capacitors; cell integration; cell transistor; easy function check mode; gigabit DRAM; landing plug contacts; low parasitic resistance device; poly metal gate technology; poly metal gates; saturation current; selective epitaxial plug scheme; stack DRAM cell; threshold voltage; Contact resistance; Dielectrics; MIM capacitors; Planarization; Plugs; Random access memory; Research and development; Threshold voltage; Tin; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-012-7

Type

conf

DOI

10.1109/VLSIT.2001.934929

Filename

934929