DocumentCode
3261937
Title
A signed digit adder with error correction and graceful degradation capabilities
Author
Cardarilli, G.C. ; Ottavi, M. ; Pontarelli, S. ; Re, M. ; Salsano, A.
Author_Institution
Dept. of Electron. Eng., Univ. of Rome "Tor Vergata", Italy
fYear
2004
fDate
12-14 July 2004
Firstpage
141
Lastpage
146
Abstract
This paper proposes a methodology to obtain fault localization and graceful degradation of a self-checking adder based on signed digit representation. The main idea underlying the paper is to exploit the fact that in signed digit arithmetic the carry operation is confined to neighbor digits. The usage of a "carry free" adder implies some advantages in terms of error detection, fault localization and repair For the detection standpoint, a parity checker can be easily applied to detect errors caused by faults belonging to the considered stuck-at fault set. Regarding the fault localization, the "carry free" property of the adder ensures the confinement of the error due to a permanent fault only to a few digits. Finally, if a fault is correctly localized, the faulty digit can be excluded and the logic which computes the other digits can be used to perform the adder operation with a reduced dynamic range.
Keywords
adders; carry logic; error correction; error detection; fault location; parity check codes; carry free adder; carry operation; error correction; error detection; fault localization; graceful degradation capabilities; parity checker; self-checking adder; signed digit adder; signed digit arithmetic; signed digit representation; stuck-at fault; Adders; Arithmetic; Circuit faults; Degradation; Dynamic range; Error correction; Fault detection; Logic; Microcontrollers; Scheduling;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2004. IOLTS 2004. Proceedings. 10th IEEE International
Print_ISBN
0-7695-2180-0
Type
conf
DOI
10.1109/OLT.2004.1319672
Filename
1319672
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