A 0.15 /spl mu/m logic based embedded DRAM technology featuring 0.425 /spl mu/m/sup 2/ stacked cell using MIM (metal-insulator-metal) capacitor

Author

Takeuchi, M. ; Inoue, K. ; Sakao, M. ; Sakoh, T. ; Kitamura, T. ; Arai, S. ; Iizuka, Tetsuya ; Yamamoto, T. ; Shirai, H. ; Aoki, Y. ; Hamada, M. ; Kubota, R. ; Kishi, S.

Author_Institution

ULSI Device Dev. Div., NEC Corp., Sagamihara, Japan

fYear

2001

fDate

12-14 June 2001

Firstpage

29

Lastpage

30

Abstract

We have developed embedded DRAM technology, in which 0.15 /spl mu/m logic transistor performance is fully compatible with that of pure logic processes. The key technology is the newly developed MIM capacitor element with W-TiN-Ta/sub 2/O/sub 5/-TiN structure. Temperatures as low as 500/spl deg/C are sufficient for the formation process for this MIM capacitor element. Excellent leakage current characteristics of 8/spl times/10/sup -15/ A//spl mu/m/sup 2/ at 125/spl deg/C with T/sub eq/ (equivalent oxide thickness) of 17 /spl Aring/ have been obtained. This technology has been actually implemented into a 4 Mbit test chip with cell size of 0.425 /spl mu/m/sup 2/. Over 50% yield without redundancy was obtained, confirming that there are no basic issues in process integration.

Keywords

CMOS memory circuits; DRAM chips; MIM devices; embedded systems; integrated circuit design; integrated circuit testing; integrated circuit yield; leakage currents; logic design; thin film capacitors; 0.15 micron; 125 C; 17 angstrom; 4 Mbit; 500 C; MIM capacitor; MIM capacitor element; W-TiN-Ta/sub 2/O/sub 5/-TiN; W-TiN-Ta/sub 2/O/sub 5/-TiN structure; cell size; embedded DRAM technology; equivalent oxide thickness; formation process temperatures; leakage current characteristics; logic based embedded DRAM technology; logic processes; logic transistor performance compatibility; metal-insulator-metal capacitor; process integration; process yield; redundancy; stacked cell; test chip; Electrodes; Insulation; Large scale integration; Leakage current; Logic; MIM capacitors; Metal-insulator structures; Random access memory; Temperature; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-012-7

Type

conf

DOI

10.1109/VLSIT.2001.934931

Filename

934931