• DocumentCode
    3261955
  • Title

    A routability constrained scan chain ordering technique for test power reduction

  • Author

    Huang, X.L. ; Huang, J.L.

  • Author_Institution
    Dept. of Electr. Eng., National Taiwan Univ., Taipei, Taiwan
  • fYear
    2006
  • fDate
    24-27 Jan. 2006
  • Abstract
    For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation during the physical design stage. In this paper, a scan chain ordering technique for test power reduction under user-specified routability constraints is presented. The proposed technique allows the user to explicitly set the routing constraints and the achievable power reduction is rather insensitive to the routing constraints. The proposed method is applied to six industrial designs. The achievable power reduction is in the range of 37-48% without violating any user-specified routing constraint.
  • Keywords
    circuit testing; network routing; network synthesis; routability constraint; scan chain ordering; test power reduction; Circuit testing; Degradation; Electronic equipment testing; Energy consumption; Energy management; Flip-flops; Integrated circuit testing; Logic testing; Routing; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 2006. Asia and South Pacific Conference on
  • Print_ISBN
    0-7803-9451-8
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2006.1594759
  • Filename
    1594759