DocumentCode
3262757
Title
Worst case execution time analysis for synthesized hardware
Author
Yoo, Jun-hee ; Feng, Xingguang ; Choi, Kiyoung ; Chung, Eui-Young ; Choi, Kyu-Myung
Author_Institution
Seoul Nat. Univ.
fYear
2006
fDate
24-27 Jan. 2006
Abstract
We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on some real-world applications show that our flow provides a fight upper bound of the execution time, and many useful hints to the designer
Keywords
embedded systems; hardware-software codesign; performance evaluation; program diagnostics; supervisory programs; fast design space exploration; hardware performance estimation flow; real-world application; software analysis; synthesized hardware; worst case execution time analysis; Algorithm design and analysis; Computer aided software engineering; Costs; Embedded system; Hardware; Performance analysis; Software algorithms; Software performance; Space exploration; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location
Yokohama
Print_ISBN
0-7803-9451-8
Type
conf
DOI
10.1109/ASPDAC.2006.1594801
Filename
1594801
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