Scaling scenario of multi-level interconnects for future CMOS LSI

Author

Yoshimura, H. ; Asahi, Y. ; Matsuoka, F.

Author_Institution

Adv. Logic Technol. Dept., Toshiba Corp., Yokohama, Japan

fYear

2001

fDate

12-14 June 2001

Firstpage

143

Lastpage

144

Abstract

Scaling guidelines for multi-level interconnects for future CMOS LSI are presented. They are based upon intensive circuit simulation combined with a 2D field solver while considering the wire length distribution of logic circuits. Interconnect structures such as metal aspect ratio and ILD thickness are optimized to minimize wiring delay without causing crosstalk problems. In addition, the scaling factors of future BEOL parameters are presented.

Keywords

CMOS integrated circuits; circuit optimisation; circuit simulation; crosstalk; dielectric thin films; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; large scale integration; 2D field solver; BEOL parameters; CMOS LSI; ILD thickness; circuit simulation; crosstalk; interconnect structures; logic circuits; metal aspect ratio; multi-level interconnects; optimization; scaling; scaling factors; scaling guidelines; wire length distribution; wiring delay minimization; CMOS logic circuits; Circuit simulation; Crosstalk; Delay; Guidelines; Integrated circuit interconnections; Large scale integration; Stochastic processes; Wire; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-012-7

Type

conf

DOI

10.1109/VLSIT.2001.934990

Filename

934990