Electrical characterization of high-k gate dielectrics

Some important issues related to the electrical characterization of high-k dielectrics will be reviewed and discussed. The problems with the conventional mobility extraction methodology for high-k gated MOSFETs will be pointed out, and an improved methodology will be demonstrated. Trapping in high-k gate dielectrics not only significantly affect electrical measurements, but also presents a serious reliability problem. Our experimental results have revealed that, in many samples, the device´s operating lifetime is limited by the trapping-induced threshold shift rather than TDDB. Since some of the trapping events can occur with a very short time constant, pulsed measurements are necessary to capture these events. A novel electrical characterization technique, named the IETS (inelastic electron tunneling spectroscopy), will be shown to be capable of revealing a wealth of information of a MOS structure, including phonon modes of both the electrodes and the gate dielectric, impurity bonding structures, and electronic traps.