Loop Parallelization Algorithm for Specific Case of Loop-carried Dependence for Hardware Compilation

This paper describes algorithm to parallelize loop with loop-carried dependency between iterations in the specific case. This algorithm can be used for hardware compilation and allows increase performance of synthesized devices. The paper represents case and condition when the suggested algorithm should be applied and introduces criterion for algorithm parameters chosen to keep up optimal balance between performance and hardware overhead. The hardware realization of ZP-coder on the base of investigated algorithm and its comparison with analogical devices are also represented.