DocumentCode
3264539
Title
Efficient management of speculative data in hardware transactional memory systems
Author
Waliullah, M.M. ; Stenstrom, Per
Author_Institution
Dept. of Comput. Sci. & Eng., Chalmers Univ. of Technol., Goteborg
fYear
2008
fDate
21-24 July 2008
Firstpage
158
Lastpage
164
Abstract
Transactional memory systems promise to simplify parallel programming by avoiding deadlock, livelock, and serialization problems through optimistic, concurrent execution of code segments that potentially can have data conflicts with each other. Data conflict detection in proposed hardware transactional memory systems is done by associating a read bit with each cache block that is set when a block is speculatively read. However, since the set of blocks that have been speculatively read - the read set - has to be maintained until the transaction commits, one can often not replace a block that has been speculatively read. This leads to poor utilization of the private caches in a multi-core system. We propose a new scheme for managing the read set in hardware transactional memory systems. The novel insight is that only the addresses of the speculatively read blocks are needed for conflict detection but not the data. As a result, there is an opportunity to reduce the space needed to keep track of speculatively read blocks by B/A, where B is the block size and A is the block address. Assuming that B is 32 bytes and A is 32 bits, there is an eightfold space saving due to this. This paper presents a novel design for leveraging this opportunity and evaluates a concept that uses a Bloom filter to hash the addresses of the read set into a structure. We find that the proposed scheme utilizes the private cache more efficiently in a typical system configuration.
Keywords
cache storage; parallel programming; transaction processing; Bloom filter; cache block; data conflict detection; hardware transactional memory system; multicore system; parallel programming; speculative data management; Computer science; Degradation; Engineering management; Hardware; Maintenance engineering; Memory management; Multiprocessor interconnection networks; Parallel programming; System recovery; Technology management;
fLanguage
English
Publisher
ieee
Conference_Titel
Embedded Computer Systems: Architectures, Modeling, and Simulation, 2008. SAMOS 2008. International Conference on
Conference_Location
Samos
Print_ISBN
978-1-4244-1985-2
Type
conf
DOI
10.1109/ICSAMOS.2008.4664859
Filename
4664859
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