A 2.0 micron BiCMOS process including DMOS transistors for merged linear ASIC analog/digital/power applications

Author

Erdeljac, J. ; Todd, B. ; Hutter, L. ; Wagensohner, K. ; Bucksch, W.

Author_Institution

Texas Instruments Inc., Dallas, TX, USA

fYear

1992

fDate

23-27 Feb 1992

Firstpage

517

Lastpage

522

Abstract

A 2.0 μm BiCMOS process incorporating 30 V bipolar, 5-50 V CMOS, precision analog elements, and 45 V power DMOS transistors with 2.0 mΩcm² R_DSON area is presented. The process is compatible with a mature mixed-signal application-specific integrated circuit (ASIC) cell library and offers fully isolated CMOS devices, providing an effective solution for intelligent analog/digital/power applications with inductive loads. This technology has been applied to the design of a 2.5 A H-bridge with supporting logic and analog control circuitry

Keywords

BiCMOS integrated circuits; insulated gate field effect transistors; mixed analogue-digital integrated circuits; power integrated circuits; 2 micron; 2.5 A; 30 V; 45 V; 5 to 50 V; BiCMOS IC; DMOS transistors; H-bridge; analog control circuitry; cell library; design; inductive loads; linear ASIC; power IC; supporting logic; Application specific integrated circuits; BiCMOS integrated circuits; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Integrated circuit technology; Isolation technology; Software libraries;

fLanguage

English

Publisher

ieee

Conference_Titel

Applied Power Electronics Conference and Exposition, 1992. APEC '92. Conference Proceedings 1992., Seventh Annual

Conference_Location

Boston, MA

Print_ISBN

0-7803-0485-3

Type

conf

DOI

10.1109/APEC.1992.228366

Filename

228366