Design of a high-speed low-power multiport register file

This paper proposes a full custom design of a 9-write and 17-read multi-port register file. The proposed register file can fulfill one read-after-write access in one system cycle with a synchronous read and an asynchronous write. The design employs a single-ended sense amplifier and a high-speed SCL address-decoder as write decoder controlled by VCLK, which is generated through a novel positive edge check circuit. The register file is implemented in SMIC 0.13 ¿m CMOS technology and passes the final verification. The post simulation results show that the write delay of the register file in the worst case is 2.5 ns and the read delay is 1.8 ns. The read-after-write timing is 2.9 ns. The power of register file is 109 mW in the worst case.