A 100MS/s recycling 2-step ADC embedding programmable gain amplification for DVB satellite

A 100 MS/s, 6-bit recycling two-step analog-to- digital converter (ADC) with an embedded programmable gain amplification function is designed in 0.18-mum CMOS, being suitable for use in digital video broadcasting - satellites (DVB-S). In the proposed ADC, a programmable gain amplifier (PGA), a sample-and-hold amplifier (SHA) as well as a multiplying digital-to-analog converter (MDAC) are combined and merged into a single switched-capacitor (SC) block, thus providing good savings in terms of power and silicon area implementation. The proposed embedded PGA function optimizes efficiency in A/D conversion according to the dynamic input signal requirement of the DVB-S application. Full transistor-level simulation is provided for the ADC with 35-dB SNDR and 41-dB SFDR at 100 MS/s, and the DNL and INL are within plusmn0.6 and plusmn0.5 LSB, respectively. The proposed ADC consumes only 12 mW from a 1.8-V power supply.