DocumentCode
3265985
Title
A novel LOP to improve the normalization of the FP adder in DSPs
Author
JianPing, Fang ; Yue, Hao ; DeLiang, Che
Author_Institution
Inst. of Microelectron., Xidian Univ., China
Volume
3
fYear
2004
fDate
18-21 Oct. 2004
Firstpage
1637
Abstract
This paper presents a novel leading-one predictor (LOP) for an SMDSP extended precision floating-point adder in digital signal processors (DSPs.). The LOP is area-efficient and has less delay overhead. The regular circuit architecture also makes it easy to design and implement in VLSI. In this paper, we mainly describe the structural and logical design of the LOP module that can be applicable to many floating-point adders.
Keywords
VLSI; adders; digital signal processing chips; floating point arithmetic; DSP adder normalization; LOP module; SMDSP extended precision floating-point adder; VLSI; delay overhead; digital signal processors; leading-one predictor; Acceleration; Adders; Circuits; Delay; Digital signal processing; Digital signal processors; Error correction; Microelectronics; Signal design; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN
0-7803-8511-X
Type
conf
DOI
10.1109/ICSICT.2004.1435144
Filename
1435144
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