An asynchronous data-path design for Viterbi decoder

Author

Bing, Shao ; Yong, Hei ; Yulin, Qiu

Author_Institution

Inst. of Microelectron., Chinese Acad. of Sci., Beijing, China

Volume

3

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

1645

Abstract

A novel asynchronous data-path design is described. Circuits for the asynchronous adder unit, asynchronous comparator unit, and asynchronous selector unit are proposed. An asynchronous data-path ACS (add-compare-select) for a Viterbi decoder is formed. The performance of the 4-bit ACS is analyzed with a novel method based on a multi-delay model. The results of performance analysis of the asynchronous 4-bit ACS show that the average case response time of 6.81 ns is only 84% of the worst-case response time, 8.08 ns. It reveals that the asynchronous data-path has some performance advantages over the synchronous one.

Keywords

Viterbi decoding; adders; asynchronous circuits; comparators (circuits); 4 bit; 6.81 ns; 8.08 ns; ACS; CMOS VLSI; Viterbi decoder; add-compare-select; asynchronous adder; asynchronous comparator; asynchronous data-path design; asynchronous selector; convolution codes; multiple-delay model; response time; Adders; Asynchronous circuits; Clocks; Convolution; Delay; Logic circuits; Maximum likelihood decoding; Performance analysis; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on

Print_ISBN

0-7803-8511-X

Type

conf

DOI

10.1109/ICSICT.2004.1435146

Filename

1435146