80 MHz MCM microprocessor/cache subsystem based on i486 architecture

Author

Sundahl, R.C. ; Aghazadeh, Milad ; Lieberman, B. ; Schreyer, T. ; Siu, Wan-Chi ; Suarez, R. ; Wilson, J.D.

Author_Institution

Intel Corp., Santa Clara, CA, USA

fYear

1992

fDate

4-6 June 1992

Firstpage

14

Lastpage

15

Abstract

An experimental multichip module (MCM) implementation of a microprocessor/cache subsystem has been designed and demonstrated to operate at 80 MHz. The module consists of an 80486DX microprocessor with a cache controller and 256 kB of second-level cache (plus parity). Thus, the integration of 16 million transistors into a single 52-cm/sup 2/ package with single-chip performance has been achieved. The high performance of the module is dependent on the architecture, the MCM technology and the complex electrical, thermal, and mechanical simulation and routing tools developed for the task.<>

Keywords

buffer storage; computer architecture; microprocessor chips; multichip modules; 256 kbyte; 80 MHz; 80486DX microprocessor; MCM microprocessor/cache subsystem; cache controller; i486 architecture; multichip module; routing tools; second-level cache; single-chip performance; Assembly; Circuit simulation; Clocks; Dielectric substrates; Dielectric thin films; Electronics packaging; Integrated circuit interconnections; Microprocessors; Power supplies; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0701-1

Type

conf

DOI

10.1109/VLSIC.1992.229259

Filename

229259