A 3.3 V 128 Mb multi-level NAND flash memory for mass storage applications

Author

Tae-Sung Jung ; Young-Joon Choi ; Kang-Deog Suh ; Byung-Hoon Suh ; Jin-Ki Kim ; Young-Ho Lim ; Yong-Nam Koh ; Jong-Wook Park ; Ki-Jong Lee ; Jung-Hoon Park ; Kee-Tae Park ; Jang-Rae Kim ; Jeong-Hyong Lee ; Hyung-Kyu Lim

Author_Institution

Samsung Electron. Co. Ltd., Kiheung, South Korea

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

32

Lastpage

33

Abstract

The NAND flash memory was originally designed to target solid-state mass storage applications. Key requirements of mass storage, low cost and high serial access throughput, have been achieved by sacrificing a non-critical feature, fast random access. For a quantum step in cost reduction, the multi-level cell is combined with NAND flash memory. This 128 Mb multi-level NAND flash memory stores two bits per cell by tight programmed cell threshold voltage (Vth) control and is made practical by significantly reducing program disturbs.

Keywords

CMOS memory circuits; EPROM; NAND circuits; 128 Mbit; 3.3 V; NAND flash memory; cost; multi-level cell; program disturbs; programmed threshold voltage control; serial access throughput; solid-state mass storage; Circuit noise; Circuit simulation; Costs; Flash memory; Latches; Pins; Solid state circuit design; Threshold voltage; Throughput; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488501

Filename

488501