• DocumentCode
    3268798
  • Title

    A 140 mm/sup 2/ 64 Mb AND flash memory with a 0.4 /spl mu/m technology

  • Author

    Miwa, H. ; Tanaka, T. ; Oshima, K. ; Nakamura, Y. ; Ishii, T. ; Ohba, A. ; Kouro, Y. ; Furukawa, T. ; Ikeda, Y. ; Tsuchiya, O. ; Hori, R. ; Miyazawa, K.

  • Author_Institution
    Device Dev. Center, Hitachi Ltd., Tokyo, Japan
  • fYear
    1996
  • fDate
    10-10 Feb. 1996
  • Firstpage
    34
  • Lastpage
    35
  • Abstract
    This 3.3 V single supply flash memory is for hand-held computers. Low bit cost is a requirement for portable use. AND flash memories have the advantages of small cell size leading to low bit cost and small program/erase size, resulting in fast efficient operation. This 64Mb flash memory is designed for serial-access flash memory cards. Memory array area is reduced by a source line plate layout. Peripheral circuit area is reduced by command/address multiplex for the input circuit, serial address comparison for the redundancy circuit, and an internal low-voltage erase circuit for the X decoder. Using the above methods, a 139.9 mm/sup 2/ chip and 67.4% cell efficiency are realized.
  • Keywords
    CMOS memory circuits; EPROM; redundancy; 0.4 micron; 3.3 V; 64 Mbit; 67.4 percent; AND flash memory; X decoder; command/address multiplex; hand-held computers; internal low-voltage erase circuit; line plate layout; portable use; redundancy circuit; serial address comparison; serial-access flash memory cards; Circuit noise; Decoding; Flash memory; Fuses; Latches; Low voltage; MOSFETs; Pins; Signal design; Switching circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-3136-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.1996.488502
  • Filename
    488502