A 98 mm/sup 2/ 3.3 V 64 Mb flash memory with FN-NOR type 4-level cell

Author

Ohkawa, M. ; Sugawara, H. ; Sudo, N. ; Tsukiji, M. ; Nakagawa, K. ; Kawata, M. ; Oyama, K. ; Takeshima, T. ; Ohya, S.

Author_Institution

NEC Corp., Sagamihara, Japan

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

36

Lastpage

37

Abstract

A 64 Mb flash memory has a multi-level cell and 64-memory-cell parallel programming. 98 mm/sup 2/ die uses 0.4 /spl mu/m CMOS and 4-levels (2b) per cell. 3.3 V operation and 6.3 /spl mu/s/B programming are achieved by using a Fowler-Nordheim (FN) NOR memory cell. Drain-voltage controlled multilevel programming (DCMP) is the key technology for simultaneous multi-level programming in the chip. To implement DCMP, a parallel multi-level verify (PMV) circuit and the compact multi-level sense amplifier (CMS), which enable a 64-memory-cells parallel programming operation (program/program verify), are used.

Keywords

CMOS memory circuits; EPROM; NOR circuits; parallel programming; 0.4 micron; 3.3 V; 64 Mbit; CMOS chip; Fowler-Nordheim NOR multilevel cell; compact multilevel sense amplifier; drain-voltage controlled multilevel programming; flash memory; parallel multilevel verify circuit; parallel programming; Collision mitigation; Differential amplifiers; Driver circuits; Flash memory; Latches; National electric code; Output feedback; Parallel programming; Registers; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488503

Filename

488503