A 100 MHz, 0.4 W RISC processor with 200 MHz multiply adder, using pulse-register technique

Author

Kozu, S. ; Daito, M. ; Sugiyama, Y. ; Suzuki, H. ; Morita, H. ; Nomura, M. ; Nadehara, K. ; Ishibuchi, S. ; Tokuda, M. ; Inoue, Yasuyuki ; Nakayama, T. ; Harigai, H. ; Yano, Y.

Author_Institution

ULSI Syst. Dev. Labs., NEC Corp., Kanagawa, Japan

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

140

Lastpage

141

Abstract

Recent emergence of various multimedia systems requires microprocessors to have features like high-performance, low power dissipation, and signal processing capabilities altogether. The 118MIPS RISC processor presented in this paper has a multiply-adder which is essential for signal processing applications. Using a pulse register and on-demand clock distribution, a 100 MHz, 428 mW 32 b RISC processor with 200 MHz multiply-adder is achieved.

Keywords

adders; digital signal processing chips; microprocessor chips; multiplying circuits; reduced instruction set computing; 0.4 W; 100 MHz; 118 MIPS; 200 MHz; RISC processor; microprocessor; multimedia systems; multiply adder; on-demand clock distribution; power dissipation; pulse register; signal processing; Clocks; Delay; Laboratories; Microprocessors; National electric code; Pipelines; Power dissipation; Pulse circuits; Reduced instruction set computing; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488544

Filename

488544