DocumentCode
3270097
Title
A 143-360 Mb/s auto-rate selecting data-retimer chip for serial-digital video signals
Author
Potson, D. ; Buchholz, A.
Author_Institution
Comlinear Corp., Fort Collins, CO, USA
fYear
1996
fDate
10-10 Feb. 1996
Firstpage
196
Lastpage
197
Abstract
Current serial digital video retimers have two limitations: (1) manufacturers are required to incorporate PCB adjustments for center frequency at each rate, and (2) auto rate selection (ARS) uses complex circuitry unnecessary for purely signal-routing applications. This circuitry, which relies on the successful detection of a de-scrambled 30 b word, operates at the clock rate and increases power dissipation. The retimer described here addresses these problems by (1) wafer trim to eliminate PCB tweaks, and (2) a simplified implementation of ARS.
Keywords
clocks; data communication; detector circuits; digital phase locked loops; timing; video signal processing; 140 to 360 Mbit/s; auto rate selection; clock rate; data-retimer chip; serial-digital video signals; wafer trim; Circuits; Clocks; Detectors; Frequency; Jitter; Phase detection; Resistors; Tuning; Voltage; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-3136-2
Type
conf
DOI
10.1109/ISSCC.1996.488568
Filename
488568
Link To Document