Design of A Low-power, High Speed Op-amp for 10bit 300Msps Parallel Pipeline ADCs

This paper presents a low-power operational amplifier suitable for the sample-and-hold (S/H) circuit with the architecture of switched-capacitor circuit .The op-amp plays an important role in the front-rank sampling module and the MDAC (multiplying D/A converter) module for the 10 bit, 300 MHz sampling rate, 4-channel parallel pipeline ADC. This paper presents a design based on optimized time-interleaved technique. By optimizing the channel sampling clock which means there is more time for the op-amp to settle up, the op-amp has a superior performance. With 3.3 V power supply, using the CSM 0.35 mum CMOS process technology, the HSPICE simulation shows that, the open-loop gain of the op-amp is 106 dB with the unity gain bandwidth of 402 MHz and the settling time is 8.8 ns, which is qualified for the requirement of the single channel sampling rate (75 MHz). The power consumption of this op-amp is only 8.57 mW, which significantly reduces the whole power of the parallel pipeline ADC.