Verification of CAM tests for input stuck-at faults

Author

Sidorowicz, Piotr R. ; Brzozowski, Janusz A.

Author_Institution

Dept. of Comput. Sci., Waterloo Univ., Ont., Canada

fYear

1998

fDate

24-25 Aug 1998

Firstpage

76

Lastpage

82

Abstract

A comparison of three tests applied to an n-word by 1-bit static CMOS content-addressable memory (CAM) array is performed with respect to the cell input stuck-at-fault model. We briefly review the methodology facilitating this comparison, and the proof of correctness of the Sidorowicz and Brzozowski test, of length 7n+2l+5, which was derived using this methodology. Then, we examine the Giles & Hunter test and demonstrate that it fails to detect bit-sa-0 and b¯i¯t¯-sa-0 faults. We also show how this test can be modified to a test, of length 11n+2l, that detects these faults. Next, we verify that the Kornachuk et al. test, which is of length 24nl and is used in BIST, detects all the faults in the fault model

Keywords

CMOS memory circuits; built-in self test; content-addressable storage; fault diagnosis; integrated circuit testing; logic testing; BIST; CAM tests verification; CMOS content-addressable memory; cell input stuck-at-fault model; input stuck-at faults; static CMOS CAM array; Built-in self-test; CADCAM; Circuit faults; Circuit testing; Computer aided manufacturing; Computer science; Electronic switching systems; Fault detection; Gas insulated transmission lines; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1998. Proceedings. International Workshop on

Conference_Location

San Jose, CA

Print_ISBN

0-8186-8494-1

Type

conf

DOI

10.1109/MTDT.1998.705951

Filename

705951