DocumentCode
3271315
Title
Robust and energy-efficient DSP systems via output probability processing
Author
Abdallah, Rami A. ; Shanbhag, Naresh R.
Author_Institution
ECE Dept., Univ. of Illinois at Urbana-Champaign, Champaign, IL, USA
fYear
2010
fDate
3-6 Oct. 2010
Firstpage
38
Lastpage
44
Abstract
This paper proposes to employ error statistics of nanoscale circuit fabrics to design robust energy-efficient digital signal processing (DSP) systems. Architectural level error statistics are exploited to generate probability or the reliability of each output bit of a DSP kernel. The proposed technique is referred to here as bit-level a posteriori probability processing (BLAPP). Energy efficiency and robustness of a 2D discrete cosine transform (2D-DCT) image codec employing BLAPP is studied. Simulations in a commercial 45 nm CMOS process show that BLAPP provides up to 14X improvement in robustness, and 25% power savings over conventional 2D-DCT codec design.
Keywords
CMOS digital integrated circuits; codecs; digital signal processing chips; discrete cosine transforms; error statistics; image coding; integrated circuit design; probability; 2D discrete cosine transform image codec; CMOS process; DSP kernel; architectural level error statistics; bit-level a posteriori probability processing; energy efficient DSP system; nanoscale circuit fabrics; output probability processing; Complexity theory; Digital signal processing; Error analysis; Hardware; Kernel; Nuclear magnetic resonance; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design (ICCD), 2010 IEEE International Conference on
Conference_Location
Amsterdam
ISSN
1063-6404
Print_ISBN
978-1-4244-8936-7
Type
conf
DOI
10.1109/ICCD.2010.5647569
Filename
5647569
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