Efficient parallel circuit simulation using bounded-chaotic relaxation

WRV256, an experimental waveform-relaxation-based parallel circuit simulator for the Victor V256 distributed-memory parallel machine, was used to study performance trade-offs between Gauss-Seidel and bounded-chaotic relaxation algorithms. Several subcircuit scheduling alternatives within the bounded-chaotic framework were also investigated. The simulator has been exercised on a suite of circuits ranging from 16000 to over 93000 FETs. Several of the circuits were extracted directly from a 16-Mb DRAM (dynamic random-access memory) memory design. It is concluded that the bounded-chaotic algorithm offers a reasonable compromise for a relaxation algorithm used for parallel machines. It offers one way to attain both the numerical efficiency of Gauss-Seidel for larger jobs and the Gauss-Jacobi parallelism for smaller ones