• DocumentCode
    3271933
  • Title

    A voting-based working set assessment scheme for dynamic cache resizing mechanisms

  • Author

    Sato, Masayuki ; Egawa, Ryusuke ; Takizawa, Hiroyuki ; Kobayashi, Hiroaki

  • Author_Institution
    Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
  • fYear
    2010
  • fDate
    3-6 Oct. 2010
  • Firstpage
    98
  • Lastpage
    105
  • Abstract
    Considering the trade-off between performance and power consumption has become significantly important in multi-core processor design. Under this situation, one promising approach is to employ a power-aware dynamic cache partitioning mechanism. This mechanism individually manages activation of each cache way, and exclusively allocates the minimum number of required ways to each thread. In the mechanism, an appropriate number of ways for a thread is decided based on locality assessment. However, sampling results of cache accesses that are used for locality assessment are disturbed by exceptional behaviors of cache accesses, which happen in a very short period. Such sampling results may change locality assessment results to ones that are not along with the overall trend in a long access-sampling period. These assessment results will excessively adapt the cache to exceptional behaviors, and deteriorate energy efficiency. To avoid such excessive adaptation by the exceptional behaviors, this paper proposes a voting-based working set assessment scheme, in which the number of activated ways is adjusted based on majority voting of locality assessment of several short sampling periods. By using the majority voting, the proposed scheme can identify the periods including exceptional behaviors, and ignore the assessment results of these periods. As a result, the proposed scheme makes the cache resizing mechanism more stable and robust. The experimental results indicate that the proposed scheme can reduce energy consumption by up to 24%, and 10% on an average without significant performance degradation in multi-thread execution on a 2-core CMP.
  • Keywords
    CMOS integrated circuits; cache storage; microcomputers; 2-core CMP; CMOS technologies; dynamic cache resizing mechanism; energy efficiency; locality assessment result; multicore processor design; multithread execution; power consumption; sampling periods; voting-based working set assessment scheme; Benchmark testing; Degradation; Energy consumption; Instruction sets; Mathematical model; Measurement; Resource management;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design (ICCD), 2010 IEEE International Conference on
  • Conference_Location
    Amsterdam
  • ISSN
    1063-6404
  • Print_ISBN
    978-1-4244-8936-7
  • Type

    conf

  • DOI
    10.1109/ICCD.2010.5647599
  • Filename
    5647599