A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle

This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs´ conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18 mum 1P6M CMOS mixed-mode technology. Simulation results show that 82 dB SNDR and 87 dB SFDR are obtained at the sampling rate of 10 MHz with the input sine frequency of 100 KHz and the whole static power dissipation is 21.94 mW