A radix-10 digit recurrence division unit with a constant digit selection function

Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, scientific, commercial, and financial applications. In this work we present a radix-10 digit recurrence division algorithm that decomposes the quotient digits into three parts and requires only the computation of five and two times the divisor. Moreover, the divisor´s multiples are selected without multiplexers and the digit selection functions are independent of the divisor´s value and do not require a lookup table. The algorithm has been synthesized and verified on a Xilinx Virtex-5 FPGA and implementation results are given.