Electromigration Avoidance Aware Net Splitting Algorithm in Analog Circuits

Electromigration caused by insufficient wire width can result in the unwanted failure of a circuit. Different from digital circuits, analog circuits may have a multitude of different current levels. It is therefore an important issue to concern about current densities in routing procedure for analog circuits, especially in the net splitting step. In this paper, we present a fast terminal tree construction algorithm taking current into account and apply simulated annealing approach to net area minimization. Experimental results show that compared with previous algorithms, our algorithm gives much smaller areas of multi-terminal nets.