• DocumentCode
    3276585
  • Title

    Fast algorithms for computing IDDQ tests for combinational circuits

  • Author

    Thadikaran, Paul ; Chakravarty, Sreejit

  • Author_Institution
    Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
  • fYear
    1996
  • fDate
    3-6 Jan 1996
  • Firstpage
    103
  • Lastpage
    106
  • Abstract
    A system to generate IDDQ tests for bridging faults (BFs) and leakage faults in combinational CMOS circuits is described. Experimental results for different sets of BPs demonstrates the efficiency and flexibility of the approach
  • Keywords
    CMOS logic circuits; automatic testing; combinational circuits; integrated circuit testing; leakage currents; logic testing; ATPG system; CMOS circuits; IDDQ tests computation; bridging faults; combinational circuits; fast algorithms; leakage faults; logic IC; Automatic test pattern generation; Central Processing Unit; Circuit faults; Circuit testing; Combinational circuits; Computational modeling; Fault detection; Genetic algorithms; System testing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1996. Proceedings., Ninth International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-7228-5
  • Type

    conf

  • DOI
    10.1109/ICVD.1996.489466
  • Filename
    489466
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3276585