Methods for dynamic test vector compaction in sequential test generation

This report presents three dynamic methods for reducing the number of test vectors for sequential circuit test pattern generation. All methods work by taking a test sequence generated by the main ATPG program for a single fault and assigning the unspecified primary inputs with specific values. The completely filled test sequence can then be shown by simulation to pick up more faults than the one for which it was generated. All three approaches are presented and discussed, with the last method justified and explained in more detail than the others. Each method has been incorporated into the FASTEST sequential automatic test pattern generator. Experimental results using many of the ISCAS-89 sequential benchmark circuits are presented for all approaches that demonstrate their effectiveness in comparison to the widely used approach of performing a single random fill on all unspecified inputs