A graph based approach to the synthesis of multi-chip module architectures

We present a graph based approach to the time (performance) constrained synthesis of multi-chip module (MCM) architectures. System-level partitioning is performed using the Stochastic Evolution heuristic, which is an effective heuristic for solving several combinatorial optimization problems. The partitioning cost function models the scheduling/allocation constraints (including interchip buses) in the form of incompatible sets. Supernodes are created using the scheduling/allocation constraints which in turn reduces the search space for the partitioner. Scheduling and resource allocation is performed for the case of time (performance) constrained synthesis and includes modeling of inter-chip buses, multi-cycle operations, pipelined functional units and functional pipelining. Efficient synthesis results are obtained for the high-level synthesis benchmarks in far less CPU time compared to the integer linear programming based model