A novel low power, variable resolution pipelined ADC

In this paper, a novel low power, variable resolution pipelined analog to digital converter (ADC) with an embedded sample and hold (S/H) circuit is presented. The ADC circuit uses a peak detector to make the resolution variable. It is capable of operating up to a sampling frequency of 200MSPS at 8-bit, 10-bit, and 12-bit resolution with a supply voltage of 2.5 V. The proposed design has DNL< ±0.25LSB, INL< ±0.5LSB, SNR of 71.5 dB and SNDR of 69.1 dB with a peak power consumption of 24 mW. The ADC is designed in thick gate process and its performance is verified in post layout simulations at 65nm technology node.