Using VHDL-based fault injection to exercise error detection mechanisms in the time-triggered architecture

As the use of dependable systems is generalising, their study in early phases of the design cycle is more and more important in order to save time and money. In this work, using a generic VEDL-based fault injection tool, called VFIT (VHDL-Based Fault Injection Tool), we have validated the dependability of a real Fault-Tolerant System using its VHDL model. The system studied is based on the Time-Triggered Architecture. It is a synchronous protocol with static scheduling that has been specifically targeted at hard real-time fault-tolerant distributed system. The use of this system is growing in aircraft and automotive areas (x-by-wire). We have analysed the pathology of the propagated errors, measured their latencies, and calculated both error detection latencies and coverages. As the main conclusion of this work, we have detected an erroneous implementation of the firmware of the controller as well as results show that built-in selftest mechanisms detect the larger part of errors.