Efficient combinational loops handling for cycle precise simulation of system on a chip

As system integration becomes a reality the need for efficient, core based, simulators is pressing. Different levels of simulation accuracy/fidelity are necessary during system design. Naturally, a system is defined as a set of communicating finite state machines. In this work, we present a cycle precise simulator that is able to efficiently handle combinational loops existing between the FSMs. We devise a strategy that ensures that the blocks that do not belong to a combinational loop will be evaluated only once per cycle, and that the order of the components within a loop tends to minimize the number of iterations required to achieve stability. We express the problem in a graph theoretic manner, and propose a set of steps to obtain a valid schedule