• DocumentCode
    3279404
  • Title

    Thermal analysis of IC package burn-in subrack

  • Author

    Khan, Navas ; Pinjala, D. ; Iyer, Mahadevan K. ; Baomin, Liu ; Mandal, Rathin ; Mui, Y.C.

  • Author_Institution
    Inst. of Microelectron., Singapore
  • fYear
    2002
  • fDate
    10-12 Dec. 2002
  • Firstpage
    366
  • Lastpage
    370
  • Abstract
    Integrated circuit (IC) package manufacturing involves number of intricate process steps and is prone to defects, which will shorten product life. Hence early deduction of the defects is important for high production yield. One of the package screening tests is the burn-in test. As the IC package power drastically increased over the last decade, the design requirements of a burn-in system to provide controlled environment is more challenging. Various techniques are employed in new generation burn-in system to reduce the burn-in time and throughput. A good thermal model and analysis of the burn-in system will help the overall IC production cause. In this paper, thermal-modeling approach of a custom built burn-in system and validation plans are discussed. Methodologies for development of compact models of package and socket, solid state heat pump and sub-rack are discussed in the paper. Emphasis is also given to validate the sub-rack level numerical models by measurements using a test package in a known ambient condition. The modeling details and validation results are discussed in this paper.
  • Keywords
    environmental stress screening; failure analysis; heat pumps; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; life testing; production testing; test equipment; thermal analysis; IC package burn-in subrack; IC package manufacturing; IC production; burn-in test; compact models; controlled environment; high production yield; package screening tests; solid state heat pump; sub-rack level numerical models; thermal analysis; thermal model; Circuit testing; Control systems; Integrated circuit manufacture; Integrated circuit modeling; Integrated circuit packaging; Integrated circuit yield; Manufacturing processes; Power system modeling; Production; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference, 2002. 4th
  • Print_ISBN
    0-7803-7435-5
  • Type

    conf

  • DOI
    10.1109/EPTC.2002.1185699
  • Filename
    1185699