DocumentCode
3279480
Title
A multiphase PLL for 10 Gb/s links in SOI CMOS technology
Author
Kossel, Marcel ; Morf, Thomas ; Baumberge, Werner ; Biber, Alice ; Menolfi, Christian ; Toifl, Thomas ; Schmatz, Martin
Author_Institution
Zufich Res. Lab., IBM Res., Ruschlikon, Switzerland
fYear
2004
fDate
6-8 June 2004
Firstpage
207
Lastpage
210
Abstract
This paper presents a multiphase PLL designed for a 10×10 Gbit/s serial link bundle that is based on a digital CDR receiver. The PLL was fabricated in a 90-nm SOI CMOS process and covers a frequency band of 9.6-12.8 GHz at a supply voltage of 1.7 V. Measurement results showed a peak-to-peak jitter of less than 0.12 UI and a power consumption efficiency of 1.5 mW/GHz per link.
Keywords
CMOS analogue integrated circuits; jitter; phase locked loops; silicon-on-insulator; synchronisation; voltage-controlled oscillators; 1.7 V; 10 Gbit/s; 9.6 to 12.8 GHz; 90 nm; CMOS analog integrated circuits; SOI CMOS technology; clock and data recovery; digital CDR receiver; high-speed integrated circuits; multiphase PLL; phase jitter; phase-locked loops; serial link bundle; voltage controlled oscillators; CMOS technology; Circuit optimization; Clocks; Jitter; Level control; Phase frequency detector; Phase locked loops; Tuning; Voltage; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE
ISSN
1529-2517
Print_ISBN
0-7803-8333-8
Type
conf
DOI
10.1109/RFIC.2004.1320573
Filename
1320573
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