DocumentCode
3281082
Title
Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multi-layer ceramic BGA
Author
Libous, J.P.
Author_Institution
CMOS ASIC Technol. Dev., IBM Corp., Endicott, NY
fYear
1996
fDate
28-30 Oct 1996
Firstpage
120
Lastpage
122
Abstract
This paper presents the simultaneous switching noise measurements, modeling, and simulation of a flip-chip CMOS ASIC test chip on a multi-layer Ceramic Ball Grid Array (CBGA) package. The modeling technique is validated by strong correlation between measurement and simulation results
Keywords
CMOS integrated circuits; application specific integrated circuits; flip-chip devices; integrated circuit modelling; integrated circuit noise; integrated circuit packaging; ball grid array package; flip-chip CMOS ASIC; multilayer ceramic BGA; simultaneous switching noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 1996., IEEE 5th Topical Meeting
Conference_Location
Napa, CA
Print_ISBN
0-7803-3514-7
Type
conf
DOI
10.1109/EPEP.1996.564804
Filename
564804
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