• DocumentCode
    3281862
  • Title

    Multi-level Logic Optimization By Implication Analysis

  • Author

    Kunz, Wolfgang

  • fYear
    1994
  • fDate
    6-10 Nov 1994
  • Firstpage
    6
  • Lastpage
    13
  • Keywords
    Automatic logic units; Circuit synthesis; Circuit testing; Combinational circuits; Cost function; Energy consumption; Fault tolerance; Integrated circuit synthesis; Logic circuits; Minimization methods;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1994., IEEE/ACM International Conference on
  • ISSN
    1063-6757
  • Print_ISBN
    0-8186-3010-8
  • Type

    conf

  • DOI
    10.1109/ICCAD.1994.629735
  • Filename
    629735
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3281862