Self-timed simultaneous bidirectional signalling for IC systems

The authors present a self-timed architectural interface design for VLSI CMOS integrated circuit systems. The interface follows a two-cycle self-timed bundled data protocol and nearly doubles the input/output (I/O) bandwidth for wide bus VLSI interprocessor communication by simultaneously sending and receiving data over the same wires. A constant overhead of four control wires is incurred over the synchronous approach proposed by K. Lam et al. (1990), as well as a decaying area penalty for increasing bus widths. This type of self-timed bundled interface can prove attractive for applications where global synchronization is difficult to achieve. The interface has been simulated for a 16-b wide bus using a quasi-analog mixed-signal Verilog approach