An Assessment of Single-Electron Effects in Multiple-Gate SOI MOSFETs with 1.6-nm Gate Oxide near Room Temperature

To allow high-temperature operation, the size of the SET needs to be further reduced (Peters et al., 1998). The suppression of short-channel effects, therefore, is especially critical to enabling single-electron tunneling at elevated temperature in the scaled MOSFET. In this work, we control the short-channel effect for devices with gate length down to 30 nm using thin oxide and multiple-gate SOI structures. We conduct an assessment of single-electron effects in our multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature