• DocumentCode
    3283910
  • Title

    Geometric bipartitioning problem and its applications to VLSI

  • Author

    Dasgupta, Partha S. ; Sen, Anup K. ; Nandy, Subhas C. ; Bhattacharya, Bhargab B.

  • Author_Institution
    Comput. Center, Indian Inst. of Manage., Calcutta, India
  • fYear
    1996
  • fDate
    3-6 Jan 1996
  • Firstpage
    400
  • Lastpage
    405
  • Abstract
    We identify a new problem called geometric bipartitioning that is useful in VLSI layout design. Given a floorplan with rectilinear modules, the problem is to partition the floor by a staircase (monotone increasing) channel from one corner of the floor to its diagonally opposite corner, such that the numbers of modules in the two halves become equal. As the partition is heavily dependent on the geometry of the floorplan, this is quite different from the classical graph bisection problem. This problem can be captured using a weighted permutation graph with integer edge weights, which may be positive, negative or zero; the goal is to find a path between two designated nodes such that the absolute value of the sum of edge weights along the path is minimum. We then show that this problem is NP-complete, and present a heuristic algorithm based on branch-and-bound. Experimental results with benchmarks and randomly generated floorplans reveal that the algorithm produces optimal results quickly most of the time. Geometric bipartitioning problem may find many applications to hierarchical decomposition, floorplanning, and routing
  • Keywords
    VLSI; circuit layout CAD; computational complexity; graph theory; network routing; search problems; NP-complete; VLSI; absolute value; branch-and-bound; classical graph bisection problem; designated nodes; edge weights; floorplan; geometric bipartitioning problem; geometry; heuristic algorithm; hierarchical decomposition; integer edge weights; layout design; monotone increasing; rectilinear modules; routing; staircase; weighted permutation graph; Application software; Constraint optimization; Costs; Delay; Geometry; Heuristic algorithms; Integrated circuit interconnections; Partitioning algorithms; Routing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1996. Proceedings., Ninth International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-7228-5
  • Type

    conf

  • DOI
    10.1109/ICVD.1996.489642
  • Filename
    489642