Design optimization of FPGA based viterbi decoder

Author

Min, Yang

Author_Institution

Dept of Electron. & Inf. Eng., Huazhong Univ. of Sci. & Technol., Wuhan, China

fYear

2011

fDate

15-17 April 2011

Firstpage

4129

Lastpage

4131

Abstract

In this paper, we propose a novel viterbi decoder in part parallel structure. The core part of the decoder-Add - Compare - Select Unit, is improved by means of pipeline. BMC (Branch Metric Computation) is improved through linear transform. TB (Trace Back) method is adopted for survivor path. The whole decoder has the advantages of speed and resource expense compared with traditional hybrid viterbi decoder. The decoder reduces combinational LUT (or register) consumption by 80% and memory blocks consumption by 50% compared with the viterbi IP core of Altera Corporation, while the former is similar to the latter in speed and BER performance. The channel rate of the decoder is up to 54Mbps on cyclone III.

Keywords

Viterbi decoding; convolutional codes; field programmable gate arrays; logic design; FPGA; Viterbi decoder; branch metric computation; combinational LUT; convolutional code; design optimization; linear transform; part parallel structure; pipeline; trace back method; Bit error rate; Cyclones; Decoding; Field programmable gate arrays; IP networks; Random access memory; Viterbi algorithm; BMC; FPGA; Viterbi; convolutional code;

fLanguage

English

Publisher

ieee

Conference_Titel

Electric Information and Control Engineering (ICEICE), 2011 International Conference on

Conference_Location

Wuhan

Print_ISBN

978-1-4244-8036-4

Type

conf

DOI

10.1109/ICEICE.2011.5777992

Filename

5777992