Delay fault testing of iterative arithmetic arrays

Delay fault testing of iterative arithmetic arrays (IAAs) is important because IAAs contain long critical paths and often determine the clock speed. A new approach, based on a weighted graph model has been developed that exploits the regularity of IAAs to select paths to be tested, and generates delay fault tests for those paths. The number of longest paths in an IAA grows exponentially with the dimension of the IAA, but the technique tests only a selected subset of longest paths, whose size is linear in the dimension of the IAA. A Monte-Carlo simulation was performed to ascertain the detection of delay faults in paths that were not explicitly tested. Promising results were obtained.<>