DocumentCode
3288892
Title
A testable static RAM structure for efficient coverage of pattern sensitive faults
Author
Su, Shyang-Tai ; Makki, Rafic Z.
Author_Institution
North Carolina Univ., Charlotte, NC, USA
fYear
1992
fDate
7-9 April 1992
Firstpage
229
Lastpage
234
Abstract
The authors present a new SRAM test technique that can reduce the test complexity from O(n/sup 2/) to 5n for detecting pattern sensitive faults. A new design-for-test scheme is employed which makes possible the use of current monitoring techniques for detecting pattern sensitivity. A simple test sequence such as a cell stuck-at test can be employed to yield the same coverage of disturbs as complex test sequences such as Gallop.<>
Keywords
SRAM chips; design for testability; fault location; integrated circuit testing; SRAM test technique; cell stuck-at test; current monitoring; design-for-test scheme; pattern sensitive faults; testable static RAM structure; Circuit faults; Circuit testing; Decoding; Electrical fault detection; Fault detection; Legged locomotion; Logic; Monitoring; Random access memory; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location
Atlantic City, NJ, USA
Print_ISBN
0-7803-0623-6
Type
conf
DOI
10.1109/VTEST.1992.232757
Filename
232757
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