DocumentCode
3288999
Title
Multiple redundancy removal during test generation and synthesis
Author
Wu, David M. ; Swanson, Robert M.
Author_Institution
IBM, Austin, TX, USA
fYear
1992
fDate
7-9 April 1992
Firstpage
274
Lastpage
279
Abstract
Techniques of multiple redundancy removal (MRFE) during test generation are described in this paper. A redundant fault, once identified, is propagated forward and backward through the sensitized paths to identify other redundant faults in the circuit under test. The technique is also applied to the class of ´dropped faults´ and ´untested faults´. This technique can also be applied to logic minimization during synthesis.<>
Keywords
logic design; logic testing; minimisation of switching nets; redundancy; logic minimization; logic synthesis; multiple redundancy removal; redundant fault; test generation; Benchmark testing; Circuit faults; Circuit synthesis; Circuit testing; Fault detection; Fault diagnosis; Logic design; Logic testing; Network synthesis; Redundancy;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location
Atlantic City, NJ, USA
Print_ISBN
0-7803-0623-6
Type
conf
DOI
10.1109/VTEST.1992.232765
Filename
232765
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