A 10-bit 100MSPS 0.35 μm Si CMOS pipeline ADC

Based on the principle of pipeline ADC, a 4-4-4-bit three-stage 10-bit pipeline analog-to-digital converter (ADC) is presented. Combining with bootstrap circuit and bottom-plate sampling technology, a high linearity on-chip sample-and-hold (S/H) is realized. The preamplifier-latch comparator of the 4-bit flash sub-ADCs is implemented to reduce the comparator latch offset by using zero-crossing technique. In order to reduce common-mode interference, clock feed-through and even order distortion, the full-differential operational transconductance amplifiers (OTA) are designed for the residue and S/H circuits. The simulation results show that this ADC achieves over 70dB SFDR with 50MHz Nyquist input frequency at 100MSample/s (MSPS). Fabricated by standard 0.35μm 2P3M mixed signal silicon CMOS process, the circuit occupies an area of 12.7mm².